interface []

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===== Proposed Future GPGPU-Sim Interface =====
**NOTE: JASON IS CURRENTLY WORKING ON THIS SOME**
  * We foresee gem5-gpu as being a
  * Since gem5 (Ruby) models the memory hierarchy, future revisions of GPGPU-Sim could more rigorously define the interface between the shader pipeline and the memories. In particular, neither the fetch or memory access (ldst_unit) pipeline stages in GPGPU-Sim export a clear API for connecting with caches. We propose a more rigorous use of pipeline registers to communicate to and from the fetch and ldst units (e.g. see gem5/src/cpu/inorder/*). These units can then be implemented either within or outside GPGPU-Sim, depending on integration aims. If the desire is to implement the fetch and/or ldst units within GPGPU-Sim but to allow tight integration with gem5, we recommend that GPGPU-Sim export the gem5 port interface (gem5/src/mem/port.*) to be connected to the gem5 memory system.
  * Specifically, the LSQPort objects in the CudaCore and the executeMemOp function belong in GPGPU-Sim. In fact, the whole CudaCore is just a thin wrapper around the GPGPU-Sim shader_core_ctx and should be eliminated as the integration between GPGPU-Sim and gem5 becomes tighter.
  * Similarly, much of CudaGPU could be moved into GPGPU-Sim.

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